Last updated: 20 November 2003

Overview

    A standard cell library has been developed using a commercial 0.25 µm, 2.5 V CMOS technology. Radiation tolerant design techniques have been employed on layout of the cells to achieve the total dose hardness levels required by LHC experiments. The library consists of digital core cell elements as well as a number of I/O pad cells.  The library cells have been fully characterised and the necessary descriptions to facilitate simulation have also been generated. The presented library features 5 times increase in speed accompanied by 26 times reduction in power consumption as well as an increase of 8 times in gate densities when compared to a  0.8 µm CMOS technology.

   A design kit that supports ASIC development on the CADENCE CAE platform has been developed. The kit offers analog and digital circuit design entry, analog simulations based on HSPICE, digital simulations based on VERILOG and mixed analog/digital simulations. To facilitate analog circuit design entry and simulation a number of analog primitive cells and parameterized cells have been prepared.  The design kit offers also the capability of logic synthesis using the SYNOPSYS design compiler as well as the use of the SILICON ENSEMBLE Place and Route tool.

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