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CERN SRAM macro

Last updated: 20 November 2003

Overview
This is a custom made synchronous dual port static memory that has been designed using a commercial 0.25μ CMOS process. Special layout design techniques has been applied to enable total dose radiation hardness compatible to the LHC experiments environment. The size and the width of the memory can be configured by putting together the necessary number of basic pre-laid out components. Thus, it can be considered as the poor man's memory generator.

The SRAM macro has been designed within the framework of the Kchip ASIC development for the CMS Preshower front end electronics.

Documentation

Verilog models

	SRAM.v This is a configurable behavioral model.
	SRAM_stimulus.v This is a stimulus for the memory model.
	waves.ps This is the simulation output waveform.

Test Results

Shmoo plots

Timing Diagrams

Power Dissipation

SEU measurements

Proton beam crossections

Submitted SRAM chips

	CERN_SRAM_1K
	CERN_SRAM_4K
	DRC waiver file for chip submissions

Papers

8th Workshop on Electronics for LHC Experiments

Presentations

	8th Workshop on Electronics for LHC Experiments
	Deep Submicron Users Group meeting (Imperial College 17/6/2002) (pdf)
	Deep Submicron Users Group meeting (RAL 12/1/2001) (pdf)
	CMS week (preshower meeting) 5/7/2001

ASIC designs using the CERN SRAM macro

	CMS Kchip Memory configuration: 2K x 18bit Detector: CMS Preshower Lab: CERN Designer: Kloukinas Kostas Status: design under submission.
	CMS FENIX chip Memory configuration: 256 x 27bit Detector: CMS ECAL Lab: RAL, CERN Designer: Bill Gannon, Magnus Hansen Status: design under submission.
	ATLAS SCAC chip Memory configuration: 128 x 18bit Detector: ATLAS tracker Lab: NEVIS Labs, Columbia University Designer: Stephan Boettcher Status: Tested O.K. For more information: http://www.nevis.columbia.edu/~atlas/electronics/asics/
	ATLAS DTMROC_S chip Memory configuration: 128 x 153 bits Detector: ATLAS TRT Lab: CERN Designer: Robert Szczygiel Status: Tested O.K.
	ATLAS MCC chip Memory configuration: 128 x 27bit Detector: ATLAS PIXEL Lab: INFN Genova Designer: Robert Beccherle Status: Tested O.K. For more Information: http://www.ge.infn.it/ATLAS/Electronics/
	ALICE AMBRA chip Memory configuration: 16K X 9 bits Detector: ALICE Silicon Drift Det. Lab: INFN Torino Designer: Gianni Mazza Status: Submitted.
	ALICE CARLOS chip Memory configuration: 256 X 9 bits Detector: ALICE Inner Tracking System Lab: INFN Bologna Designer: Alessandro Gabrielli Status: Work in progress.
	LHCb SYNC chip Memory configuration: --- X -- bits Detector: LHCb Muon System Lab: INFN Cagliari Designer: Adriano Lai Status: Work in progress.